Flash EEPROM cells ahve recently been developed to allow the erasure of the charge on the floating gates of several EEPROM memory cells at once. A description of such a cell may be found in F. Masuoka, et al., "A New Flash E.sup.2 PROM Cell Using Triple Polysilicon Technology," IEDM 84, page 464. Flash E.sup.2 PROM cells are advantageous over prior structures in that the time for a memory erase is considerably reduced.
Texas Instruments Inc. has recently developed an X-cell technology for EPROM cells. X-cell arrays of this type typically comprise a plurality of memory cells formed at a face of a semiconductor layer in rows and columns. Common sources are provided for each of four memory select transistors that are arranged around each common source in an "X" pattern. A single contact is made to each common source region.
The X-cell configuration reduces the required array area needed by conventional structures by up to 20%. These structures typically consist of common source and drain regions that are each shared by only two select transistors.
Up to this point, an X-cell layout for an electrically-erasable, programmable read-only memory (EEPROM) array has not been developed. A need has therefore arisen in the industry for a EEPROM array that combines the advantages of flash erasing with the compactness of an X-cell array.